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MC10EP139, MC100EP139 3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip
The MC10/100EP139 is a low skew /2/4, /4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 mF capacitor. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the /2/4 and the /4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation.
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20 20 1 TSSOP-20 DT SUFFIX CASE 948E 20 20 1 SOIC-20 DW SUFFIX CASE 751D HEP KEP XXX A L,WL Y, YY W, WW MCXXXEP139 AWLYYWW HEP or KEP 139 ALYW 1
1 = MC10EP = MC100EP = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week
* Maximum Frequency > 1.0 GHz Typical * 50 ps Output-to-Output Skew * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * * * * * *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2005
1
February, 2005 - Rev. 6
Publication Order Number: MC10EP139/D
MC10EP139, MC100EP139
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
Table 1. PIN DESCRIPTION
PIN CLK*, CLK* EN* FUNCTION ECL Differential Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Differential B2/4 Outputs ECL Differential B4/5/6 Outputs ECL Frequency Select Input B2/4 ECL Frequency Select Input B4/5/6 ECL Frequency Select Input B4/5/6 ECL Positive Supply ECL Negative Supply
1 VCC
2 EN
3 DIVSELb0
4 CLK
5 CLK
6 VBB
7 MR
8 VCC
9 DIVSELb1
10 DIVSELa
MR* VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa* DIVSELb0* DIVSELb1 VCC VEE
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View)
*Pins will default low when left open. DIVSELa Q0 CLK CLK /2/4 R Q0 Q1 Q1
EN
Q2 /4/5/6 R Q2 Q3 Q3
MR DIVSELb0 DIVSELb1 VEE
Figure 2. Logic Diagram
Table 2. FUNCTION TABLES
CLK Z ZZ X EN L H X MR L L H Function Divide Hold Q0:3 Reset Q0:3
Z = Low-to-High Transition ZZ = High-to-Low Transition
DIVSELa L H DIVSELb0 L H L H DIVSELb1 L L H H
Q0:1 Outputs Divide by 2 Divide by 4 Q2:3 Outputs Divide by 4 Divide by 6 Divide by 5 Divide by 5
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MC10EP139, MC100EP139
CLK Q (/2) Q (/4) Q (/5) Q (/6)
Figure 3. CLK and OUTPUT Timing Diagram
CLK tRR RESET
Q (/n)
Figure 4. Timing Diagram
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MC10EP139, MC100EP139
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 100 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 758 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C TSSOP-20 TSSOP-20 TSSOP-20 SOIC-20 SOIC-20 SOIC-20 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 90 60 33 to 35 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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MC10EP139, MC100EP139
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 65 2165 1365 2090 1365 1790 2.0 1890 Typ 82 2290 1490 Max 105 2415 1615 2415 1690 1990 3.3 Min 65 2230 1430 2155 1460 1855 2.0 1955 25C Typ 83 2355 1555 Max 105 2480 1680 2480 1755 2055 3.3 Min 65 2290 1490 2215 1490 1915 2.0 2015 85C Typ 84 2415 1615 Max 105 2540 1740 2540 1815 2115 3.3 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Input HIGH Current Input LOW Current 0.5 Min 65 3865 3065 3790 3065 3490 2.0 3590 Typ 82 3990 3190 Max 105 4115 3315 4115 3390 3690 5.0 Min 65 3930 3130 3855 3130 3555 2.0 3655 25C Typ 83 4055 3255 Max 105 4180 3380 4180 3455 3755 5.0 Min 65 3990 3190 3915 3190 3615 2.0 3715 85C Typ 84 4115 3315 Max 105 4240 3440 4240 3515 3815 5.0 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. All loading with 50 W to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP139, MC100EP139
Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 8)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Input HIGH Current Input LOW Current 0.5 Min 65 -1135 -1935 -1210 -1935 -1510 -1410 Typ 82 -1010 -1810 Max 105 -885 -1685 -885 -1610 -1310 0.0 Min 65 -1070 -1870 -1145 -1870 -1445 -1345 25C Typ 83 -945 -1745 Max 105 -820 -1620 -820 -1545 -1245 0.0 Min 65 -1010 -1810 -1085 -1810 -1385 -1285 85C Typ 84 -885 -1685 Max 105 -760 -1560 -760 -1485 -1185 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) Input HIGH Current Input LOW Current 0.5 Min 70 2155 1355 2075 1355 1775 2.0 1875 Typ 83 2280 1480 Max 100 2405 1605 2420 1675 1975 3.3 Min 70 2155 1355 2075 1355 1775 2.0 1875 25C Typ 87 2280 1480 Max 105 2405 1605 2420 1675 1975 3.3 Min 75 2155 1355 2075 1355 1775 2.0 1875 85C Typ 90 2280 1480 Max 110 2405 1605 2420 1675 1975 3.3 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 12. All loading with 50 W to VCC - 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP139, MC100EP139
Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 15) Output LOW Voltage (Note 15) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) Input HIGH Current Input LOW Current 0.5 Min 70 3855 3055 3775 3055 3475 2.0 3575 Typ 85 3980 3180 Max 100 4105 3305 4120 3375 3675 5.0 Min 70 3855 3055 3775 3055 3475 2.0 3575 25C Typ 90 3980 3180 Max 105 4105 3305 4120 3375 3675 5.0 Min 75 3855 3055 3775 3055 3475 2.0 3575 85C Typ 95 3980 3180 Max 110 4105 3305 4120 3375 3675 5.0 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 15. All loading with 50 W to VCC - 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 17)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 18) Output LOW Voltage (Note 18) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) Input HIGH Current Input LOW Current 0.5 Min 70 -1145 -1945 -1225 -1945 -1525 -1425 Typ 85 -1020 -1820 Max 100 -895 -1695 -880 -1625 -1325 0.0 Min 70 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 90 -1020 -1820 Max 105 -895 -1695 -880 -1625 -1325 0.0 Min 75 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 95 -1020 -1820 Max 110 -895 -1695 -880 -1625 -1325 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC - 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP139, MC100EP139
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
-40C Symbol fmax tPLH, tPHL tRR ts th tPW tSKEW tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 5 Fmax/JITTER) Propagation Delay Reset Recovery Setup Time Hold Time Minimum Pulse Width EN, CLK DIVSEL, CLK CLK, EN CLK, DIVSEL MR CLK, Q (Diff) MR, Q 550 700 200 200 400 100 200 550 Min Typ >1 700 800 100 120 180 50 140 450 50 200 0.2 150 110 800 180 100 300 < 1.0 1200 250 150 125 800 900 600 700 200 200 400 100 200 550 Max Min 25C Typ >1 750 850 100 120 180 50 140 450 50 200 0.2 800 190 100 300 < 1.0 1200 275 150 150 900 1000 675 800 165 200 400 100 200 550 Max Min 85C Typ >1 825 950 100 120 180 50 140 450 50 200 0.2 800 215 100 300 < 1.5 1200 300 975 1100 Max Unit GHz ps ps ps ps ps ps ps mV ps
Within Device Skew Q, Q Device-to-Device Skew (Note 21) Random Clock Jitter (RMS) (See Figure 5 Fmax/JITTER) Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% - 80%) Q, Q
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 21. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.
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900 800 VOUTpp (mV) 700 600 5 500 400 300 200 100 0 4 3 2 1 8 7 6 JITTEROUT ps (RMS) JITTEROUT ps (RMS)
900 800 VOUTpp (mV) 700 600
500 400 300 200 100 0 4 3 2 1
EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE EE EE
(JITTER) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz)
Figure 5. B2, Fmax/Jitter
8 7 6 5
EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE EE EE
(JITTER) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz)
Figure 6. B5, Fmax/Jitter
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900 800 VOUTpp (mV) 700 600 5 500 400 300 200 100 0 4 3 2 1 8 7 6 JITTEROUT ps (RMS) JITTEROUT ps (RMS)
900 800 VOUTpp (mV) 700 600
500 400 300 200 100 0 4 3 2 1
EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE EE EE
(JITTER) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz)
Figure 7. B4, Fmax/Jitter
8 7 6 5
EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE EE EE
(JITTER) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz)
Figure 8. B6, Fmax/Jitter
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MC10EP139, MC100EP139
Zo = 50 W
Q Driver Device Q
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC10EP139DT MC10EP139DTR2 MC10EP139DW MC10EP139DWR2 MC100EP139DT MC100EP139DTR2 MC100EP139DW MC100EP139DWR2 Package TSSOP-20 TSSOP-20 SOIC-20 SOIC-20 TSSOP-20 TSSOP-20 SOIC-20 SOIC-20 Shipping 75 Units / Rail 2500 / Tape & Reel 38 Units / Rail 1000 / Tape & Reel 75 Units / Rail 2500 / Tape & Reel 38 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC10EP139, MC100EP139
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP139, MC100EP139
PACKAGE DIMENSIONS
SOIC-20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE G
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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MC10EP139, MC100EP139
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE B
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E
2X
L/2
20
11
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. ICONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC10EP139/D

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